Kaushik Roy

Kaushik Roy photo

Dr. Roy is the Edward G. Tiedemann Jr. Distinguished Professor of Electrical and Computer Engineering at Purdue University, where he joined the faculty in 1993. He was previously with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He received his Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. Dr. Roy received the 2005 SRC Technical Excellence Award, the SRC Inventors Award, the Purdue College of Engineering Research Excellence Award, and the 2010 IEEE Circuits and Systems Society Technical Achievement Award. He is a Fellow of the IEEE. His research interests include spintronics, device-circuit co-design for nano-scale silicon and non-silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 600 papers in refereed journals and conferences, holds 15 patents, graduated 56 Ph.D. students, and is co-author of two books on low power CMOS VLSI design.


1. M. Sharad, G. Panagopoulos, and K. Roy, “Spin-neuron for ultra low power computational hardware,” Device Research Conference, June 2012, pp. 221-222.
2. M. Sharad, C. Augustine, G. Panagopoulos, and K. Roy, “Spin-based neuron model with domain wall magnets as synapse,” IEEE Trans. Nanotech. 11, 843 (2012).
3. R. Venkatesan, V. Kozhikkottu, C. Augustine, A. Raychowdhury, K. Roy, and A. Raghunathan, “TapeCache: A high density, energy efficient cache based on domain wall memory,” IEEE International Symposium on Low Power Electronics and Design, July/August, 2012.
4. M. Sharad G. Panagopoulos, C. Augustine, and K. Roy, “NLSTT-MRAM: robust spin transfer torque MRAM using non-Local spin injection for write,” Device Research Conference, June 2012, pp. 97-98.
5. S. Park, S. Gupta, N. Mojumder, A. Raghunathan, and K. Roy, “Future cache design using STT MRAMs for improved energy efficiency: devices, circuits, and architecture,” ACM/IEEE Design Automation Conference, June 2012, pp. 492-497.
6. C. Augustine, A. Raychowdhury, B. Behin-Aein, J. Tschanz, V. K. De, and K. Roy, “Numerical analysis of domain wall propagation for dense memory arrays,” IEEE Electron Devices Meeting (IEDM), December 2011.
7. C. Augustine, G. Panagopoulos, B. Behin-Aein, A. Sarkar, S. Srinivasan, and K. Roy, “Low-power functionality enhanced computation architecture using spin-based devices,” Nanoarch 2011, pp. 129-136.
8. C. Augustine, N. N. Mojumder, X. Fong, H. Choday, S. P. Park and K. Roy, “Spin-transfer torque MRAMs for low power memories: prospects and perspective,” IEEE Sensors Journal 12, 756 (2012).
 
 
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